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| Exhibiting ChipTimer, Timing Closure Tool, 20-200% speed-up, 10% area reduction using special techniques and custom CellOpt generated libraries; SolutionWare, Cell, IO and Memory Characterization-Modeling for Timing, Power, SI, CCS and ECSM; automatic verification including memories; CellOpt, timing and power Optimizer for cells and simple blocks like adders and multipliers; YieldOpt, statistical process variation analyzer which does away with SSTA and Monte-Carlo; PowerTeam: dynamic gate level power Verilogbased simulator using special libraries generated by SolutionWare; UnBlock/RcBack for custom block modeling and RC back-annotation. |