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Session 4C

Wednesday 3/22/00

1:25pm - 3:10pm

 

Low Power Design and Test

 

Co-Chairs: Kaushik Roy, Purdue University, Vamsi K. Srikantam, Hewlett Packard

 

1:25pm

Introduction

1:30pm

4C.1 Achieving Low-power Design Through Lowering Voltage From Device Level To Software Level (Invited)

Takayasu Sakurai, University of Tokyo, Tokyo, Japan

1:55pm

4C.2 Peak Power Reduction in Low Power BIST

Xiaodong Zhang and Kaushik Roy, Purdue University, West Lafayette, IN

2:20pm

4C.3 Low Power BIST for Wallace Tree-based Fast Multipliers

D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos and G. Alexiou, University of Patras, Patras, Greece

2:45pm

4C.4 Probabilistic Bottom-up RTL Power Estimation

Ricardo Ferreira*, AM Trullemans*, Jose Costa** and Jose Monteiro**, *DICE Universite Catholique de Louvain, Belgium, **IST/INESC, Lisboa, Portugal


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International Symposium on Quality of Electronic Design
Copyright 1998 ISQED. All rights reserved.
Revised: May 13, 2001 .