Session 1A

 

10:30am - 12:00pm

 

Reliability and Design in Deep Sub-micron Technologies

 

Co-Chairs

Farid Najm, University of Toronto

Ajith Amerasekera, Texas Instruments

 

10:30am          

Introduction

 

10:35am          

1A-1            Reliability Evaluation for Integrated Circuit with Defective Interconnect under Electromigration, Xiangdong Xuan, Adit Singh1, Abhijit Chatterjee, Georgia Institute of Technology, Atlanta, GA and 1Auburn University, Auburn, AL        

 

11:05am          

1A-2            Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs, Amir Ajami, Kaustav Banerjee1, Massoud Pedram2, Amit Mehrotra3, Magma Design Automation, Cupertino, CA, 1University of California at Santa Barbara, CA, 2University of Southern California and 3University of Illinois at Urbana-Champaign, Urbana, IL                   

 

11:35am          

1A-3            Random Sampling for On-Chip Characterization of Standard-Cell Propagation Delay, Stefano Maggioni, Andrea Veggetti, Alessandro Bogliolo1, Luigi Croce, STMicroelectronics, Agrate, Italy and 1University of Urbino, Urbino, Italy     

 


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