Session 1B

 

10:30am - 12:00pm

 

Reducing Leakage Currents in VLSI Circuits

 

Co-Chairs           

Payam Heydari, University of California, Irvine

Khorram Muhammad, Texas Instruments

 

10:30am          

Introduction

 

10:35am          

1B-1            Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains, Afshin Abdollahi, Farzan Fallah1, Massoud Pedram, University of Southern California, Los Angeles, CA and 1Fujitsu Laboratories of America, Sunnyvale, CA

 

11:05am          

1B-2            Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic, Geun Rae Cho and Tom Chen1, Colorado State University, Fort Collins, CO and 1Hewlett Packard, Fort Collins, CO     

 

11:35am          

1B-3    Design Techniques for Gate-Leakage Reduction in CMOS Circuits, Rafik Guindi, Farid Najm, University of Toronto, Toronto, Ont., Canada           

 


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