Session 2A

1:00pm - 3:05pm

 

Testing of SoCs

 

Co-Chairs

Sreejet Chakravarty, Intel Corporation

Jacob Abraham, University of Texas

 

1:00pm

Introduction

 

1:05pm

2A-1    Solving the SoC Test Scheduling Problem Using Network Flow and Reconfigurable Wrappers, Sandeep Koranne, Tanner Research Inc., Pasadena, CA 

 

1:35pm

2A-2    Static Pin Mapping and SOC Test Scheduling for CORES with Multiple Test Sets, Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar Reddy1, Mentor Graphics Corp., Waltham, MA and Wilsonville, OR, 1University of Iowa, Iowa City, IA           

 

2:05pm

2A-3            Compact Dictionaries for Fault Diagnosis in BIST, Chunsheng Liu, Krishnendu Chakrabarty, Duke University, Durham, NC   

 

2:35pm

2A-4            Automated Synthesis of Configurable Two-Dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns, Chien-In Henry Chen, Wright State University, Dayton, OH

 


Home| Conference| Committee| Sponsors| Resources| Archive| News

International Society for Quality Electronic Design (ISQED Org.)
Copyright 1998-2003 ISQED. All rights reserved.
Revised: January 31, 2003