Session 3A

3:30pm - 5:30pm

 

Interconnect and Substrate Noise

 

Co-Chairs

Sarma Vrudhula, University of Arizona

Amit Majumdar, Sun Microsystems

 

3:30pm

Introduction

 

3:35pm

3A-1    Post-Route Gate Sizing for Crosstalk Noise Reduction, Murat Becer,   David Blaauw1, Ilan Algor2,             Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim Hajj3, Motorola Inc., Austin, TX, 1University of    Michigan, Ann Arbor, MI and 2Motorola Semiconductor Israel Ltd., Israel, 4University of Illinois, Urbana, IL        

 

4:05pm

3A-2    Noise Aware Driver Modeling for Nanometer Technology, Xiaoliang Bai, Rajit Chandra1, Sujit Dey, Prasanna Srinivas1, University of California, San Diego, La Jolla, CA and 1Magma Design Automation, Cupertino, CA      

 

4:35pm

3A-3            Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics, Tom Chen, Amjad Hajjar1, Hewlett Packard, Fort Collins, CO and 1Colorado State University, Fort Collins, CO     

 

4:50pm

3A-4            Modeling Crosstalk Induced Delay, Chung-Kuan Tsai, Malgorzata Marek-Sadowska, University of California, Santa Barbara, CA

 

5:05pm

3A-5    A CAD-Oriented Modeling Approach to Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design, Hai Lan, Zhiping Yu, Robert Dutton, Stanford University, Stanford, CA   

 

 


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