Session 4A

10:30am - 12:00pm

 

Power Analysis and Low Power Design

 

Co-Chairs

Rajiv Joshi, IBM

Alireza Keshavarzi, Intel Corporation

 

10:30am

Introduction

 

10:35am          

4A-1            Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers, Soroush Abbaspour, Massoud Pedram, Payam Heydari1, University of Southern California, Los Angeles, CA and 1University of California-Irvine, Irvine, CA

           

11:05am          

4A-2    Cycle-Accurate Energy Measurement and High-Level Energy Characterization of FPGAs, Hyung Gyu Lee, Sung Yuep Nam, Naehyuck Chang, Seoul National University, Seoul, Korea   

 

11:35am          

4A-3            Quantifying Error in Dynamic Power Estimation of CMOS Circuits, Puneet Gupta, Andrew Kahng, University of California at San Diego, La Jolla, CA         

 

11:50am          

4A-4            Monolithic DC-DC Converter Analysis and MOSFET Gate Voltage Optimization, Volkan Kursun, Siva Narendra1, Vivek De1, Eby Friedman, University of Rochester, Rochester, NY and 1Intel Corp., Hillsboro, OR  

 


Home| Conference| Committee| Sponsors| Resources| Archive| News

International Society for Quality Electronic Design (ISQED Org.)
Copyright 1998-2003 ISQED. All rights reserved.
Revised: March 11, 2003