Session 4B

10:30am - 12:00pm

 

Topics in Device and Interconnect Modeling

 

Co-Chairs

Janet Wang, Cadence Design Systems

Amit Mehrotra, University of Illinois, Urbana

 

10:30am

Introduction

 

10:35am          

4B-1            Analysis of Simultaneous Subthreshold and Gate-Oxide Tuneling Leakage Current in Nanometer CMOS Design, Wesley Kwong, Dongwoo Lee, David Blaauw, Dennis Sylvester, University of Michigan, Ann Arbor, MI

 

11:05am          

4B-2    Design and Analysis of Low-Voltage Current-Mode Logic Buffers, Peyam Heydari, University of California, Irvine, CA

 

11:35am          

4B-3            Reduced-Order Modeling Based on PRONY's and SHANK's Methods via the Bilinear Transformation, Makram Mansour, Amit Mehrotra, University of Illinois at Urbana-Champaign, Urbana, IL      

 


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