Session 5A

1:00pm - 3:05pm

 

Timing and Noise Issues in Physical Design

 

Co-Chairs

Tanay Karnik, Intel Corporation

Rajiv Murgai, Fujitsu

 

1:00pm

Introduction

 

1:05pm

5A-1    Clock Scheduling for Power Supply Noise Suppression Using Genetic Algorithm with Selective Gene Therapy, Wai-Ching Douglas Lam, Cheng-Kok Koh, Purdue University, West Lafayette, IN       

 

1:35pm

5A-2            Minimizing Inter-Clock Coupling Jitter, Ming-Fu Hsiao, Malgorzata Marek-Sadowska1, National Taiwan University, Fremont, CA and 1University of California, Santa Barbara, CA

 

2:05pm

5A-3    A Proposal for Routing-Based Timing-Driven Scan Chain Ordering, Puneet Gupta, Stefanus Mantik1, Andrew Kahng, University of California at San Diego, La Jolla, CA and 1Cadence Design Systems, Inc., San Jose, CA  

 

2:20pm

5A-4    A False Agressor Elimination Method Using Functional Relationship for Full-Chip Crosstalk Analysis, Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong, Samsung Electronics Co., Ltd., Gyeonggi-do, Korea 

 

2:35pm

5A-5    PDL: A New Physical Synthesis Methodology (Invited), Rajeev Murgai, Fujitsu 

 


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