Session 4C

10:30am - 12:00pm

  Layout and design techniques for quality and reliability

  Co-Chairs

Marco Casale-Rossi, ST Microelectronics
Tanay Karnik, Intel

  10:30am          

Introduction

     

10:35am          

4C-1    A High Performance SIMD Framework for Design Rule Checking on Sony's PlayStation 2 Emotion Engine Platform, Sandeep Koranne

 

11:05am          

4C-2    Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells
Tetsuya Iizuka, Makoto Ikeda, and Kunihiro Asada

 

11:35am          

4C-3    Buffered Clock Tree for High Quality IC Design
Rishi Chaturvedi and Jiang Hu

 


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