Session 5B

1:00pm - 3:05pm

 Low power design

Co-Chairs

David Overhauser, Cadence
Dennis Sylvester, University of Michigan

 

1:00pm

Introduction  

1:05pm

5B-1    Power Supply Optimization in sub-130 nm Leakage Dominant Technologies
Man L Mui, Kaustav Banerjee and Amit Mehrotra

 

1:35pm

5B-2    Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for Sub-130nm CMOS Technologies
Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy

 

2:05pm

5B-3    Low Power and High Performance Circuit Techniques for High Fan-in Dynamic Gates Ge Yang, Zhongda Wang, and Sung-Mo Kang

 

2:20pm

5B-4    Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis Kushwinder Jasrotia, Jianwen Zhu


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