With recent advance of VLSI design, interconnect delay plays dominant role in the chip performance. X-Architecture, which is based on pervasive use of 0-degree, 45-degree, 90-degree and 135-degree-oriented wiring, has been proposed to achieve high-performance by reducing wire length and via count. In this paper, a buffer planning algorithm at floorplanning stage for X-Architecture is proposed. Firstly, the concept of Feasible Region (FR) is extended to X-Arch Feasible Region (XFR) by which buffer regions for a net in X-Arch can be determined. Then, a new buffer insertion algorithm using shortest-path model is applied with consideration of X-Arch routing congestion. At last, dead space redistribution is performed to optimize timing performance and congestion.