In this paper we report a comprehensive set of statistical static timing (SSTA) studies performed on a UMC test chip manufactured at 90nm process node. We employed extensive variation extraction techniques to prepare a complete set of input variation data for the technology node. Our studies include SSTA runs in the presence of various process variation components, comparison of SSTA results to those obtained from traditional corner flows, and statistical optimization to improve parametric yield of the design. We observed that generally traditional corner methodologies produce more pessimistic results than those obtained from the SSTA. We also noticed that it is hard to guarantee pessimism in the traditional analyses, unless all the process corner combinations are sampled.