A 8b 10Ms/s Low Power Pipelined A/D Converter

Bi Yuan,  Yi Zhang,  Lili He
San Jose State University


Abstract

This paper describes an 8-bit, 10 M Samples/second analog to digital converter, with 2V fully differential input range, which is implemented in TSMC 0.25Ám CMOS technology. It achieves low power dissipation of 25mW, and the chip area is 0.56mm2. Measured performance yields a very good VTC curve and a sine wave fitting curve for 200KHz input at 10Msample/s, DNL testing of -0.2LSB~0.75LSB; INL testing of -0.2LSB~0.65LSB, 44.62dB of SNDR (signal to noise plus distortion ratio) and ENOB of 7.12 bits.