Recent progress in the fabrication of three-dimensional integrated circuits that stacks multiple die connected with high-density interconnects, has opened up the possibility of exploiting this technology to alleviate performance and power related issues raised by interconnects in nanometer CMOS. Physical synthesis for three-dimensional integrated is substantially different from traditional planar integrated circuits due to the presence of additional constraints of placing circuit blocks in multiple die. To realize the full potential offered by three-dimensional integrated circuits, a high-level synthesis for these circuits must take layout-related issues unique to 3D technology into account during the synthesis process. We present a 3-D layout-aware binding algorithm for high-level synthesis. We propose a simulated annealing algorithm that tightly integrates the synthesis tasks of resource binding, assignment of modules to multiple die, 3-D floorplanning, and inter-die via minimization. Since floorplanning and resource binding are inter-dependent, the algorithm can significantly outperform traditional high-level synthesis flows that seperate these tasks. Compared to a traditional 3-D layout-unaware binding, experiments show that our approach can improve the total wirelength by 29% on average, while the longest netlength is reduced by 21%. In addition, the number of inter-layer via count is reduced by 27%. These optimizations are achieved with no penalty in chip area.