System Level Estimation of Interconnect Length in the Presence of IP Blocks

Taraneh Taghavi,  Ani Nahapetian,  Majid Sarrafzadeh
University of California, Los Angeles (UCLA)


Abstract

With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-scale circuits. Up to now, the proposed techniques for wirelength estimation in the presence of IP blocks approached this problem either in a flat framework based on the geometrical structure of the circuit or in a hierarchical framework based on uniform distribution property for standard cells. In this paper, we propose a technique for hierarchical derivation of wirelength estimation in the presence of single and multiple blockages using Rentís parameter of the circuit by assuming non-uniform probability distribution for standard cells. To measure the accuracy of our estimation, we compared our results with the results of placement and routing using a commercial CAD tool. The results illustrate that in the presence of multiple IP blocks, the average error of our technique is less than 8%, as compared to its counterparts with the average error of 35% and 150%.