In this paper, we propose a switch-level substrate noise simulation tool named SilcVerify for high-speed memory design based on nano-scaled CMOS processes. It uses the device switching model (DSM) as its noise macro and the adjacent geometry dependent macromodel (AGDM) as its substrate macro. The DSM represents the noise injection of each transistor into the substrate. It consists of one current source and one capacitance. The AGDM is a scalable model based on the layout geometry and Voronoi tessellation. Consequently, a sparse network composed with DSMs and AGDMs is solved by using a linear system solution technique with the efficiency of run time and capacity. Experimental results for real circuits using lightly-doped DRAM processes verify that SilcVerify can simulate three orders larger circuits and two orders faster than the reference method using a 3-D substrate model and a non-linear circuit simulator while maintaining the accuracy of about 10% error. Currently, we are using SilcVerify in the step of block placement and guard-ring optimization for PLL jitter reduction.