This paper describes the implementation of a passive RFID tag targeting low power implementation, which works on 915 MHz UHF frequency. The tag implements an innovative and efficient synchronization algorithm, which deals with significant reference clock variations. The proposed architecture allows customizing the command sets implemented inside its digital block, according to the target application needs, saving area and reducing power consumption. A flexible design flow is proposed for the customization, verification and synthesis of the digital. The tag has been fully tested and validated at several simulation levels, and the synchronizing algorithm performed according to the expected. The resulting design has been sent to a foundry. Field tests are going to be performed on the chip, and a new and re-validated design version will be sent to the foundry for commercial production in large scale.