A new six transistor (6T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stability and the integration density of FinFET memory circuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced by utilizing PMOS access transistors. The read stability is enhanced by 60% while reducing the leakage power by 21% as compared to a standard tied-gate FinFET SRAM cell with the same size transistors. One gate of each pull-up FinFET of the cross-coupled inverters is permanently disabled in order to achieve write-ability with minimum sized transistors. The proposed independent-gate FinFET SRAM circuit with P-type data access transistors reduces the idle mode leakage power, the read power, the write power, and the cell area by 61%, 20%, 11.4%, and 17.5%, respectively, as compared to a standard tied-gate FinFET SRAM cell sized for similar read stability in a 32nm FinFET technology.