As the relative levels of coupling capacitance in smaller process geometries and of process variations caused due to lithography, CMP, and Etch process increases, process variation aware coupled noise analysis is becoming more important especially at under 45nm design and below. We propose a method to simulate crosstalk noise for the worst process corner cases. Our method considers a spatial correlation for transistor length variations because the difference of the driver strength between victim and aggressor is the main source of the variation. Both lithography and CMP variation are first considered separately and combined to show crosstalk noise change for interconnect variations. We compare results for various process variation models using a crosstalk test structure. In these simulation studies, crosstalk noise without variation consideration underestimates by up to 17% the noise of the proposed worst corner model.