As CMOS technology scales continually, interconnect power has become a significant part of total chip power. Without compromising the circuit performance, timing slacks can be utilized to optimize interconnect power efficiently. The optimization of total interconnect power is affected not only by the properties of each interconnect as well as the timing constraint, but also by the topology of the circuit. In this paper, we introduce a novel slack distribution algorithm IPOSA to optimize interconnect power efficiently. A piecewise linear model is proposed to quantify the relationship between interconnect power reduction and timing slack amount, considering the interconnect length and the switching activity. Monte Carlo analysis shows our piecewise model is accurate enough that the average error is 1.7%. Based on the piecewise linearity of the model, we propose an iterative slack distribution algorithm which minimizes total interconnect power with given timing constraint. The experimental results show that our algorithm can achieve 41.7% interconnect power reduction on average.