As part of copper (Cu) damascene manufacturing process, Chemical Mechanical Polishing (CMP) has been applied to keep the uniformity of metal thickness, and the planarity of chip/wafer to accommodate today’s shrinking lithography process window. CMP is a process that heavily depends on the metal width and density, and there is a strong interaction between design and CMP process. Dummy fills (tiling) are routinely applied to the design files to keep metal density uniform. However, due to complex natures of CMP process (pad, slurry and metal/oxide interaction, long range and multi-level effects), CMP related hotspots are often observed in the manufacturing process. CMP related issues such as Cu pooling/bridging and excessive thickness variation will have a major impact on chip yield and circuit timing and performance. Thus it is essential to correct those hotspots during circuit design stage for better yield and performance. In this paper we will introduce the use of an accurate physical based model to simulate CMP process on a full chip level and detect CMP related hotspots. We will show by using Cadence CMP Predictor (CCP), hotspots that are related to the tiling approach were detected. The CMP model can then be used to assist developing optimal tiling approach and reduce or eliminate CMP related hotspots, hence help to enhance the yield of the designs. The unique capability of detecting CMP related hotspot accurately has made CCP a valuable tool in the design flow to improve yield and performance.