The two main forces pushing package technologies to a new frontier are size and cost. The need of the hour is miniaturization, fuelled by rapidly growing complexity in the wireless phone market. CSP (Chip Scale Packaging)having already reached 100%, further miniaturization can be achieved only by 3D packaging techniques.Complex 3D packaging techniques have hit the roadmap and SoC design is largely driven by the co-dice that are stacked and the package elements such as size, routing layers, ball count etc. wherein “package-die co-design” is extremely critical for on time product delivery. In fact,it is not surprising that a SoC’s floorplan is driven by package and “co-design” is an understatement. This paper highlights the importance of package –die codesign for early package closure in SIPs. Guidelines and solutions on the Periphery and package planning are included. Careabouts and tradeoffs when designing SIPs are also explained.