Electrostatic discharge, the transfer of charge between bodies that alters device characteristics has become a major reliability concern in the semiconductor industry. Conventional approaches of using ESD testers to detect ESD defects are post-fabrication methods which leave narrow design time for ESD rectification. This paper discusses a CAD approach which captures ESD problems in the design phase enabling designers to build robust ESD structures. The discussed verification platform performs ESD simulations on the design and aids designers to locate and debug the potential ESD failure nodes in the circuit. This approach leads to robust ESD designs with minimal cycle-time and reduces silicon re-spins. ESD protection mechanisms are built with the main objective to shunt ESD currents through predefined harmless discharge paths. To locate and fix the appropriate current paths that might fail for ESD is therefore one of the prime aspects of ESD design. An early detection of potential ESD failures assists in redesigning protection circuit appropriately. An automated process that mimics the actual analysis heuristics followed by designers in locating the high-impedance paths could speedup the debug process. The discussed simulation based circuit probing mechanism renders to the designers various electrical characteristics at key circuit points and would also aid designers in re-aligning or modifying the ESD protection circuitry.