We propose a novel dependable SRAM with 7T memory cells, and introduce a new concept, "quality of a bit (QoB)" for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode, assignment of information is as usual as one memory cell has one bit. On the other hand, in the high-speed or dependable mode, one-bit information is stored in two memory cells, which boosts the speed or increases the reliability. By carrying out Monte Carlo simulation of dynamic cell stability in a 90-nm process technology, we confirmed the advantage of the proposed SRAM.