Inductive fault analysis techniques examine the physical geometry of a design to identify potential defect sites. Since traditional methodologies for test generation, fault simulation, and diagnosis rely on logic-level models of the circuit under test, the behavior of a circuit node within a standard cell is not easily modeled since it does not always map directly to a logic-level signal. A significant percentage of defects, however, involves these internal nodes and therefore cannot be ignored. We propose a methodology to create a mapping between the physical nodes of a standard cell and the logic level. By identifying appropriate fault activation and error propagation conditions for each internal node, accurate fault models can be formulated. Simulation results show that coverage of bridge faults involving internal nodes is as low as 32% for a stuck-at test set.