Speed-up of ASICs derived from FPGAs by Transistor Network Synthesis Including Reordering

Abstract

This paper presents a method for speeding-up ASICs by transistor reordering. The proposed method can be applied to a variety of logic styles and transistor topologies. The rationale of the obtained gains is explained through logical effort concepts. When applied to circuits based on 4-input networks, which is the case of many structured-ASIC or FPGA technologies, significant performance gains are obtained at a small area expense. This observation points out that our method can be of special interest when migrating FPGAs to ASICs.