As the IC feature size advances to nanometer, IR drop and power network noise produce significant effects on delay and signal integrity. Traditional timing analysis and closure should not be regarded as complete without taking into consideration voltage fluctuation on the PG net-work. Moreover, the interaction between the timing and IR drop makes this issue more complicated. At the gate level, timing and PG rail analysis need to perform several iterative loops until they come to converge. Whenever the supply voltage changes, the conventional approach of moment-based timing calculation needs to re-compute from scratch. However, the variation of the power supply does not affect signal nets and only changes the electrical properties of driving and fan-out gates. Based on this observation, we propose a new method to efficiently calculate timing. This method can update timing from arithmetic operations based on results in the previous iteration rather than the time-consuming tree traversal.