Integrated circuits today rely on extensive re-use of precharacterized IP bocks and macro cells to meet the demand for high performance system on chip (SoC). In this paper we propose a methodology for characterization of IP blocks and macro cells for statistical timing analysis considering process variations and spatial correlations. We develop efficient models for capturing both inter-die and intra-die variations in devices and interconnects. Increasing variability of the process parameters in subnanometer designs requires instance-specific characterization of these design blocks. We propose a technique for instance-specific calibration of pre-characterized timing model. The suggested model was created for large industrial designs in 65nm technology and validated against SPICE for accuracy. This is the first work which deals with timing macromodeling of IP blocks and macro cells considering process variations.