Integrated circuit manufacturability in DSM is directly dependent on how well the manufacturing variations are accounted for during the design of circuits. This paper reviews the effect of various process variations in DSM especially systematic and random variations in three process generations 90nm, 65nm & 45nm by doing SPICE simulation and analysis to look at the derating factors depending on the sensitivity to variations. Few individual standard cells are studied as a part of this exercise to see the effect of variation on their delays. Analysis suggested the variations are doubling in each process generations and an overall 5% increase in the derating factor from process to process. Random variations began to dominate the overall variations for smaller geometries. Signing off the design by choosing right corners for applying the correct derating factor is very much needed and calls for a rethink in the scan shift & capture methodologies, clock network design, design methodologies and analysis for timing closure. Analysis suggests the need for selective, location based and variation aware guardbanding in future designs for better performance and higher yields.