Sampling Error Estimation in High-Speed Sampling Systems Introduced by the Presence of Phase Noise in the Sampling Clock

Salam Marougi
Agilent Technologies


Abstract

The presence of phase noise in the sampling clock of fast Analog-to-Digital converters introduces time jitter into the sampling instants of the Analog-to-Digital converter. In this paper, an analysis has been performed to quantify the impact of phase perturbation in the sampling clock on the signal-to-noise ratio of the digitized waveform. Close form formulae have been obtained for the signal-to-jitter noise (S/Njit) ratio when the phase perturbation is random as well as when it is dominated by a periodic and deterministic component. The result obtained is then used to predict the jitter noise generated by a sampling clock with typical phase noise performance. The results obtained will help identify the impact of the various sampling and phase noise parameters on the resulting S/Njit ratio.