As VLSI technologies progress to nanometer scales, process variations become important and cause significant impact on circuit performance. The proactive management of process variation during the design process is critical to ensure effective device yield and to keep manufacturing costs down. This requires the calculation and application of margins that account for the design's required specifications (e.g. operating frequency) across multiple corners (voltage supply and process) and in all device modes. The $RLCK$ parasitics cause further performance degradations. Parasitics must be taken into account during the initial design cycle. In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A current-starved voltage controlled oscillator (VCO) is treated as a case study and to the best of the authors' knowledge, this is the first VCO design that accounts for both parasitic degradation and process variation together. The physical design of the VCO is carried out in a generic $90 nm$ Salicide 1.2V/2.5V 1 Poly 9 Metal process design kit. The oscillation frequency is the objective function with the area overhead as constraint. A performance degradation of $43.5\%$ is observed when the parasitic extracted circuit was subjected to worst case process variation. After a single physical design iteration, the frequency of oscillation was within $4.5 \%$ of the target.