Clock skew scheduling for peak current reduction is a conventional technique for solving IR-drop problem in physical design stage. In this paper, we propose two kinds of long delay flip-flops and a heuristic algorithm that is used to resynthesize flip-flops of a circuit. Because the switching times of flip-flops in the resynthesized circuit are staggered, the IR drop effect can be reduced. Unlike clock skew scheduling, our technique not only can be used in physical design stage but also in logic design stage. The other advantages of our technique over the clock skew optimization technique are that ours has less area overhead and has more opportunities to find a better result. Experimental results show that our technique can reduce peak current and dropped voltage up to 42.8% and 38.6%, respectively.