Abstract--As process geometries are shrinking, width of the metal layer is continuously decreasing, height of the layer and wire lengths are increasing, thereby increasing the effect of coupling capacitances. Coupling induced crosstalk may induce unwanted noise on coupled signal nets resulting in functional failure and performance degradation and becomes a significant limitation in achieving first pass silicon success. At the same time the complexity of noise analysis has significantly increased due to factors such as driver weakening, IR drop, power network switching, voltage scaling and variations in manufacturing processes. Therefore validating the capabilities and verifying the analysis of a crosstalk analysis tool for current and future process nodes is very critical for efficient and accurate signoff analysis. The modeling of the cell itself needs to be accurate and comprehensive. Accurate analysis of special cells without additional library requirements. An efficient propagation methodology and identifying true violation sources to reduce design cycle time and pessimism. A complete hierarchical solution is useful to analyze large designs. Accuracy, runtime and CPU resources for characterization, considering, one-time library characterization v/s on-the-fly for the required design cells. The objective of the paper is to share the methodology and challenges involved in Crosstalk Noise Analysis and how the Composite Current Source (CCS) based Crosstalk Noise Analysis capability of PrimeTime SI would help us achieve many of our goals.