The main goal of this paper is to study the delay evolution for future technology nodes (32nm and beyond) using electrical circuit predictive simulations. In this aim, two SPICE predictive models, directly based on ITRS data, are developed respectively for devices and interconnects. The predictive spice models generation is presented and validated versus 45nm silicon data. The predictive delay evaluation is performed with buffered interconnect lines simulations. The simulation results show that critical interconnect length should be in the order of 10µm for the 2020 generation. Moreover, in forthcoming technologies, drives resizing as well as systematic buffer insertion should not be any longer systematic issues to limit wire delays increase.