On-Chip Process Variation Detection and Compensation using Delay and Slew-Rate Monitoring Circuits

Amlan Ghosh1,  Rahul Rao2,  Ching-te Chuang2,  Richard Brown1
1University of Utah, Salt Lake City, UT 84112, 2IBM TJ Watson Research Center, Yorktown Heights, NY 10598


Abstract

In the nm design era, post-fabrication process characterization and compensation have become extremely important for mitigating the impact of process variations on the parametric yield. In this paper, a new variation detection and compensation scheme is presented that uses both slew and delay metrics to gauge the drive-strengths of and mismatch of NMOS and PMOS devices. The importance of considering both of these metrics is illustrated. Four compensation schemes are analyzed, based on delay or slew as the detection metric, with the ability to apply forward and reverse body-biasing. Design considerations, simulation results and power-performance characteristics of these schemes in a 45 nm SOI technology are presented. These schemes are shown to be capable of adjusting the critical path delay of the die to within the desired 3% of the nominal delay while reducing the total power dissipation by an average of ~8% across various process corners.