The rapidly reducing time-to-market a design and the increased importance of speed in microprocessor circuits are calling for novel design-automation algorithms. A major challenge in the design of microprocessor circuits is transistor sizing in dynamic CMOS logic due to increased number of channel-connected transistors on various paths of the design, and increased magnitude of process variations. This paper proposes a process variation aware transistor sizing algorithm for dynamic CMOS logic. The efficiency of this algorithm is illustrated first by a 2-b weighted binary-to-thermometric converter, of which the critical path delay was optimized from 355 ps to 157 ps which accounts for a 55.77% delay improvement, and the delay uncertainty due to process variation was optimized by 60.75%. A 4-b unity weight binary-to-thermometric converter was also tested, of which the critical path delay was optimized from 152 ps to 103 ps which account for a 32.23% delay improvement, and delay uncertainty due to process variation was optimized by 63.6%. Applying the proposed timing optimization algorithm to a mixed-dynamic-static CMOS 64-bit adder, the critical path delay was optimized to 632 ps and the power-delay-product is optimized to 84.17 pJ.