Standard cell library based design methodology has been widely adopted in ASIC design industry to shorten time-to-market. In this methodology, maintaining multiple driving strength for each gate type is critical since it allows efficient timing closure with low power. However,due to formidable burden on library designers, often only few gate implementations are available for many gate types.The problem becomes more dfficult if constructing accurate delay tables is considered. This imposes a great challenge on efficient cell library design. This challenge is tackled in this paper. We propose a fast cell characterization approach for parameterized cell library. By our approach, the layout and the delay table of any integer-sized cell can be accurately generated solely from the smallest cell without any additional simulations. Thus, dense cell library can be efficiently generated. As a result, significant area can be saved by the synthesis using the dense library compared to the sparse cell library which is often the case in practice.