In this paper, an efficient parallel analysis flow for the design of the full power distribution network (PDN) in both frequency and time domain is proposed which includes the impact of the voltage regulator model. Based on the experimental results we demonstrate that including the voltage regulator model in the PDN model increases the transient voltage drop in the PDN where in nanoscale ICs it could not be ignored. We customize the flow to speedup simulation time of the micro seconds slow response time of the off chip voltage regulator. The flow is parallelized using MPI to reduce the CPU time. The work highlights the power integrity issues related to regulator and low, mid and high frequency ranges. The parallel flow results show speedup of up to 22 times with single processor and more than 430 times using up to 200 processors over HSPICE transient simulation for 5 to 10 stacked layers. The PDN simulation time is reduced from hours to less than a minute.