We are proposing an on-chip technique to dynamically detect and eliminate worst-case crosstalk pattern (4Cc and 3Cc) induced delay in bus-based macro-cell designs. The crosstalk patterns are classified as 4Cc, 3Cc, 2Cc, and Cc based on Miller coupling effect (MCF). The proposed technique implements a crosstalk pattern detection unit to detect the occurrence of worst-case crosstalk patterns by comparing the data transmitted in previous cycle with the data to be transmitted in current cycle. On detection of worst-case crosstalk pattern the transmission of current data is postponed for one clock cycle and instead bus lines are reset to ensure that the impact of signal transition pattern on coupling capacitance is always 2Cc or less. Experimental results on four HLS benchmarks shows that the proposed technique provides an average performance improvement of 23% with 3% increase in bus area overhead compared to designs without proposed on-chip technique. Experimental results on on-chip microprocessor buses simulated with SPEC2000 benchmark suite  shows an average performance improvement of 43% over designs without proposed technique with 3% increase in bus area.