We propose a novel design flow for mismatch and process-variation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an $8 \times 8$ APS array is designed using the proposed methodology for $32nm$ CMOS technology. Performance metrics such as power, output voltage swing, dynamic range (DR) and capture time (delay) have been measured. The baseline results show a power consumption of $16.32\mu W$, output voltage swing of $428mV$, dynamic range ($DR$) of $59.47dB$ and a capture time of $5.65\mu s$. The baseline APS array is subjected to $5\%$ ``intra-pixel'' mismatch and $10\%$ ``inter-pixel'' process variation and the effect on power and output voltage swing has been observed. The APS array is subjected to a design and analysis of Monte Carlo experiments based optimization. Using this approach, we have been able to achieve $21\%$ reduction in power (including leakage). To the best of our knowledge, this is the first ever nano-CMOS implementation of an APS array optimized to be mismatch and process variation tolerant.