The substrate coupling noise (SCN) can cause the retention time failure of DRAM cells through junction leakage in storage nodes when the data bits are loaded to signal lines simultaneously. To simulate this core SCN for the data variations, and to design the optimal guard-ring minimizing it, we propose an advanced SCN simulation flow using a hierarchically separated substrate modeling. Using this on a 65nm DRAM core technology, we present a simulation-based core guard-ring design guide and its best topology for the used technology considering the area cost. We expect this method and guard-ring design guide will play an important role in DRAM core design as the device density becomes higher and the scaling-down of technology becomes more aggressive.