A New Low Power Test Pattern Generator Using a Variable-Length Ring Counter

Bin Zhou1,  Yi-zheng Ye1,  Zhao-lin Li2,  Xin-chun Wu1
1Microelectronics Center,Harbin Institute of Technology, 2Tsinghua University


Abstract

A new built-in self-test (BIST) test pattern generator (TPG) for low power testing is presented in this paper. The principle of the proposed approach is to reconfigure the CUTís partial-acting-inputs into a short ring counter (RC), and keep the CUTís partial-freezing-inputs unchanged during testing. Experimental results based on ISCASí85 and ISCASí89 benchmark circuits show that 17% reductions in the test data storage, 43% reductions in the number of test pattern, 30% reductions in the average power, 19% reductions in the average power and 46% reductions in the total power consumption are attained during testing with a small size decoding logic.