Electronic System Level (ESL) is regarded as a necessary solution to deal with the ever increasingly complex System-on-Chip (SoC) design. Most ESL designs are modeling at the C high level language (no matter functional C or SystemC). Although some commercial products are partially available, the lack of directly translating C or SystemC into RTL becomes a main obstacle to a seamless ESL flow from high level abstraction through RTL and all the way to the final chip design. We propose an efficient semi-hardware description language called VeriC (Verilog and C) to bridge ESL and RTL. Like SystemC, VeriC is based on C++ and not only describes the design by a syntax very close to Verilog, but also it can model the target design at both pin and cycle accuracy with an implicit clock mechanism, a modeling way closer to Verilog. Those VeriC modules can be directly translatable to RTL and also can be interoperable with other modules in C/SystemC/Verilog languages by hybrid simulation. Our objective is not to replace SystemC, but to move the RTL model up to a higher level such that detailed cycle-accurate implementation can be present even in C-level simulation, a supplemental and more efficient approach for bridging the gap between ESL design and RTL models. Experimental results show that the VeriC simulation speed can be 2-10X faster than SystemC, because of the improvement in the simulation kernel (by taking advantages of input/output connections and a simpler cycle mechanism). It can also reach 10X-250X simulation speedup than Verilog in simulating the same behavior.