This paper concerns the circuit and architecture design of diode-switch phase change memories at highly scaled technology nodes. Due to its great scalability potential, phase change memory technology has recently attracted tremendous interest, and from storage density perspective the diode-switch phase change memory cell structure is highly desirable. Design of very high density diode-switch phase change memory faces at least two challenges at circuit and architecture levels, including (i) silicon area overhead of memory peripheral circuits must be minimized in order to push the effective storage density envelope, and (ii) conventional defect tolerance strategy using redundant row/column repair may no longer be applicable and new defect tolerance approach should be used. This paper presents possible solutions to address the above two issues. Very simple and cost-effective peripheral circuits including row/column decoders and sensing approach are developed, and a theoretical analysis of the impact of non-negligible reverse-bias diode leakage is also presented. Moreover, this paper presents a simple defect tolerance approach that combines coarse-grained redundancy repair and error correcting codes (ECC). Hypothetical memory design examples are further used to demonstrate the presented design techniques.