In this paper, we propose a generalized V-shaped multilevel floorplanning method with consideration of fixed-outline constraint. The Sequence Pair is used as the floorplan representation. The proposed multilevel method adopts a two-stage structure: top-down partitioning and floorplanning followed by bottom-up merging and refinement. At the first stage, we recursively partition and floorplan the circuits until there are limited number blocks in each sub-circuit. Since we use a multi-partitioning instead of bi-partitioning, general non-slicing floorplan structures are explored in each level, which potentially cause more effective exploration of the solution space. At the second stage, using a multilevel sequence pair structure, we recursively merge the sub-circuits into bigger circuits and do the refinement. Compared with IMF, Capo 10.2 and IARFP, the proposed method obtained the best results under fixed-outline constraints and, compared with IARFP, it achieved 2.67x speedup and 9\% wirelength reduction on average.