It is typically not feasible to provide zero Defective Parts per Million (DPPM) for majority of applications due to the high test costs. Comprehensive functional tests to find all detectable faults have large test times, resulting in a prohibitive cost. Statistical tools are used in the industry for digital testing to optimize the test cost and DPPM by real-time analysis. Our goal is to propose an Analog to Digital Converter Built in Self Test scheme which has compatibility with similar dynamic optimization measures. Multiple variants of Very Low Cost ATE have been developed for digital testing which rely on relaxed timing, power or tester channel requirements to lower hardware cost. Systems containing mixed-signal/RF components typically can not be tested on such ATE due to limitations/lack of analog/RF stimulus and measurement modules on VLC-ATE. This paper proposes a hybrid BIST scheme for ADCs to enable full production-quality testing as well as reduced coverage testing with VLC-ATE in conjunction with statistical analysis tools. We cover on-chip stimulus generation for a fully functional at-speed test as well as for a low-cost-reduced-coverage approach. Results for the BIST scheme are presented along with a discussion on implementation feasibility and merits.