Peak power consumption during test for the low power devices is a major concern. Huge peaks in the instantaneous power consumption will result in high rates of change of current (di/dt) causing adverse noise effects like VDD-drop and ground-bounce. Also, a high frequency of occurrence of high di/dt may cause severe decrease in the reliability of the circuit. Hence the process of testing low power devices must be peak power aware. This paper provides a method to minimize the peak power during speed capture phase by partitioning the nodes into two zones based on their timing slacks. One of the zones contains the timing-critical nodes, while the other contains the non timing-critical ones. Each zone may be split into multiple bins. Test patterns are generated independently for each bin targeting the nodes belonging to that bin alone, thus reducing the size of the target set. It is very important that the peak power consumed by the test patterns for each bin in the timing-critical zone is well within the tolerable limit. This approach allows the designer to have a better control over each pattern and also helps to minimize the effects of high peak power and high di/dt.