An Innovative Method to Automate the Waiver of IP-Level DRC Violations

John Ferguson,  Sandeep Koranne,  David Abercrombie
Mentor Graphics


Intellectual property (IP) blocks often contain known design rule checking errors that have been “waived” by the foundry, meaning they acknowledge the error as a design rule violation, but do not consider it to be a critical yield-limiting defect. Because this waiver information is not conveyed in any consistent manner with the IP, waived IP design rule violations that reappear when the IP is integrated into a full-chip design must typically be investigated as though they are new violations. This paper will review various historic methods used to identify waived errors at the chip level, then propose a new automated method for identifying and eliminating waived errors, allowing chip designers to achieve accurate design rule checking results while minimizing debug time.