Designers are moving toward Chip Multiprocessors (CMPs) due to the increasing demand for higher processing power. In a multi-core system, power and performance may be dynamically traded off by utilizing power management (PM). This paper addresses the problem of minimizing the total power consumption of a chip multiprocessor system while maintaining a target average throughput. The proposed solution relies on a hierarchical framework, which employs core consolidation, coarse-grain dynamic voltage and frequency scaling (DVFS), and task assignment at the CMP level and fine-grain DVFS based on closed-loop feedback control at the individual core level. Experimental results show an average of 23% power saving compared to a baseline technique, and demonstrate the high efficacy of the proposed hierarchical PM framework.